There are two primary approaches to the design of large-periphery Metal-Oxide-Semiconductor (MOS) Transistors; one relies on cascading (or arraying) column of multi-Legs (or multi-Fingers) Gates in parallel to enable delivering the required high output current. The other utilizes one single-legged device having sufficiently large Gate width that enables it to deliver same or similar amount of output current. Major advantage of the former approach is that it ensures a desired “Square-like” footprint for any particular large-periphery Transistor Layout. This provides more ease and flexibility in designing and laying-out such Large-periphery Transistors in any given Integrated-Circuit (IC). It also reduces the total device Gate Resistance, and hence it can boost the device power-gain and Bandwidth. The drawback can come however from an excessive increase of the Capacitive parasitic's with the increase of number of Legs (due to the increase of Gate-to-Drain and Gate-to-Source overpasses, and the Gate-to-Bulk parasitic's). This can still impose constraining limit on the device operations at relatively higher frequencies (GHz range) when the number of Legs becomes sufficiently high. Such hit on the Transistor Bandwidth from the multi-Legs Gate designs was described and demonstrated in the work of Kwangseok Han, Jeong-hu Han, Minkyu Je and Hyungcheol Shin, “RF Characteristics of: 0.18-μm CMOS Transistors”, Journal of the Korean Physical Society, vol. 40, no. 1, pp. 45-48, January 2002. It arises simply because the resulting increase of the Capacitive parasitic's in the large-periphery multi-Legs MOS Transistor can outweigh its enhancement to Bandwidth that comes from the reduction of its Gate Resistance. A compromise is often sought in laying such very large-periphery devices that are specifically aimed to deliver high output currents. It optimizes the width of the Gate-Legs in a Multi-Legs MOS device such that it best balances the effects from its total capacitive parasitic's to those of its total equivalent Gate resistance. This technique for Layout optimization was described in the work of: Troels Emil Kolding., “Consistent Layout Techniques for Successful RF CMOS Design”, RF Integrated Systems and Circuits (RISC) Group, Aalborg University, Denmark.
Despite their higher switching-speed (Bandwidth) from the effective suppressions of Junction-Capacitances, the Large-periphery multi-Legs Transistors that are based on Silicon-On-Insulator (SOI) technology can carry more Bandwidth sensitivity with increasing Gate-to-Drain and Gate-to-Source overpasses and higher Gate-to-Bulk parasitic's. While the Junction-Capacitances in the Bulk MOS Transistors scale with the increase of total number of Gate-Legs and can therefore buffer the effects from the corresponding increase of the overpass-Capacitances, these Junction-Capacitances are suppressed in the SOI-MOS and consequently the switching-speed in these devices reduces more pronouncedly with the increase of total number of Gate-Legs. This consequently causes these multi-Legs SOI-MOS devices to naturally favor for higher performance the Layouts that incorporate MOS structures with wider Gate-Legs and reduced number of Legs. Furthermore the total equivalent Gate resistance in these SOI-MOS devices reduces substantially even with just a few wide Gate-Legs, or only a one wider Gate-Leg, when the Metal-Gates replace PolySilicon-Gates.
A whole major issue does arise however with SOI-MOS Transistor designs that incorporate wider Gate-Legs. It is their higher susceptibility to Bipolar latch-up because of their substantially higher Impact-Ionizations currents that are generated around their Drains (the Impact-Ionizations current per Leg scales with widening the Gate-Leg). This is especially true for the case of Fully-Depleted-SOI (FD-SOI) MOS Transistor that inherently possesses an already lowered Body-to-Source barrier through which the Impact-Ionizations current conducts and lowers it further to cause this latch-up. This tendency for latch-up in FD-SOI MOS was first reported in the work of C. Fenouillet-Beranger et al., “Parasitic bipolar impact in 32 nm undoped channel Ultra-Thin BOX (UTBOX) and biased Ground Plane FDSOI high-k/metal gate technology”, Solid-State Electronics, vol. 74, pp. 32-37, 2012.
Such effects from the parasitic Bipolar are especially damaging in the integrated Electronics that operate in high radiation environments (high aviation altitudes, outer Space, etc. . . . ). When these Transistors are biased at their maximum nominal magnitudes for highest performance, energetic cosmic-rays that can strike even their ultra-thinned Sensitive Silicon Volumes (e. g case of ultra-thin FD-SOI MOS Transistors) can induce a much added charge that can cause substantial further lowering of their Body-to-Source lateral barriers therefore resulting in many different functional failures or malfunctions (e. g. Single-Event-Burnout, Single-Event-Latch, Single-Event-Upset, Single-Event-Transient, Single-Bit-Upset, Multiple-Bit-Upset, Single-Event-Functional-Interrupt); all these modes of failures or malfunctions are commonly referred to as: Single-Event-Effects (SEE's). It was specifically demonstrated by P. E. Dodd et al., “Single-Event-Upset and Snapback in Silicon-on-Insulator Devices”, Sandia National Laboratories, Albuquerque, N. Mex., March 2000, that a combined effect from Impact-Ionizations due to high biasing and from Single-Event-Effects due to the Cosmic rays does drastically amplify these failures (by factor close to 6.5). While the other effects from Cosmic rays that still damage the Electronics, such as Total-Ionization-Dose (TID), typically take quite long time (months or even years) to build their damage on the MOS dielectrics and slowly and gradually drift the device performance, the SEE's on the other hand do and can cause an instantaneous and swift failure when they are not very adequately guarded against. Most recent major incident caused by SEE's is the 2008 Cosmic-ray showers on the commercial passenger airline QF72 that prevented it from accurately processing its Angle-of-Attack data. One crew member and eleven passengers suffered serious injuries, while eight crew members and ninety-five passengers suffered minor injuries.
A very adequate Device-level protection against the SEE's can reduce or may even totally eliminate the need for the Redundant-circuitries that are always employed nowadays in all the avionics and the Space electronic systems to tackle the SEE's. This can substantially reduce the die area of integrated-circuits and sensors as well as their power consumptions. It can also enable their more practical deployment everywhere and anywhere (e. g. in more tiny spaces and closer to other integrated modules). It can also pave the way for denser system-level integrations that may include much added on-chip functionalities.
The classical fix to this Bipolar latch-up has traditionally been through incorporating a Body-Tied-Source (BTS) implant within the Source-diffusion. This BTS is very highly doped and with same dopant type as the device Body. This allows it to filter the Impact-Ionizations current away from the lateral Body-to-Source barrier and hence preventing the bipolar latch-up. This approach was well explained in the work of K. Hirose et al., “Analysis of Body-Tie Effects on SEU Resistance of Advanced FD-SOI SRAMs Through Mixed-Mode 3D Simulations”, IEEE Trans. Nucl. Sc., vol. 51, no. 6, pp. 3349-3353, December 2004.
Two main issues still exist with this approach:                1—The low electric conductivity of the Body (especially in FD-SOI) that the Impact-Ionizations current sees to BTS can still cause Bipolar latch. This is because a high voltage-drop develops in this Body from the conducting Impact-ionizations current that sees this low electric conductance in Body. This had only recently been addressed through U.S. Pat. No. 9,741,857 B2 (Aug. 22, 2017).        2—The “effective” peripheral width of the Transistor (and therefore its drive current) gets reduced relative to the total footprint of the device layout. This is because the addition of this BTS region consumes from the Source-diffusion volume and reduces it. A set of design-rules that alleviate for given bias and device periphery this reduction from the total “effective” width of the Transistor were formulated and defined already through same Patent: U.S. Pat. No. 9,741,857 B2.However no absolute closed-form (or complete) fix to the above still exists to date.        